IC Layout Senior Engineer

Startup Talents · United States · posted today ago

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About this role

This is a remote position.

ROLE DETAILS :

Industry:manufacturer of Microprocessors with embedded AI

Location :Remote EU or France (Paris) with occasional travel to Head Office

Markets :Worldwide/Internationational

Minimum expérience :3 years

Environnement : Cadence tools : Virtuoso and other tools from the Cadence suiteFine Element analysis tools like Altair SImSolid, Ansys Mechanical, HyperWorks, Femap, ANSYS, Abaqus, Patran, SimScale. Techniques : Layout automation, Analog layout, analog and mixed-signal circuits, floorplans, block-level layouts, process design rules, ADC Layout, DAC Layout,Languages : English (mandatory), French is a plus but not mandatoryYour manager : the R&D Director MISSIONSAs a Layout Engineer within the Analog IC team you will :Lead the layout of custom ICs and analog components while developing automation tools.Design and implement custom layouts for analog and mixed-signal circuits, including custom analog and RF components, while minimizing parasitic effects to enhance the DC and AC precision of analog signals.Create floorplans and block-level layouts for high-performance analog systems.Ensure alignment with process design rules and foundry specifications.Collaborate with foundry engineers to resolve layout-related issues during manufacturing.Develop and utilize custom scripts or tools to efficiently automate repetitive layout tasks.

Profil

Extensive experience with the physical layout of ADCs, DACs, and other mixed-signal components. Demonstrated success in completing complex layouts across various node sizes. In-depth expertise in analog layout techniques, including device matching, parasitic minimization, and noise isolation strategies. Proficiency with Cadence tools. Experience in post-layout simulation using FEM tools. Experience with layout automation is a plus. Experience in Advanced node required (experience in GF 22FDX is highly valued.